1. Field of the Invention
The present invention relates to a volume apparatus formed of semiconductor resistors and semiconductor switches.
2. Description of the Prior Art
FIG. 3 is a circuitry of a conventional volume apparatus. In the figure, designated 1 is an input terminal, and 2 a semiconductor voltage dividing circuit which consists of semiconductor resistors 2.sub.1, 2.sub.2, . . . , 2.sub.n connected in series, with the semiconductor resistor 2.sub.1 connected to the input terminal 1 and the semiconductor resistor 2.sub.n grounded.
Denoted 3 is a semiconductor switch circuit which consists of semiconductor switches 3.sub.1, 3.sub.2, . . . , 3.sub.(n+1). One end of the semiconductor switch 3.sub.1 is connected to a connection point between the input terminal 1 and the semiconductor resistor 2.sub.1 ; one end of the semiconductor switch 3.sub.2 is connected to a connection point between the semiconductor resistor 2.sub.1 and the semiconductor resistor 2.sub.2 ; . . . and one end of the semiconductor switch 3.sub.(n+1) is connected to a connection point between the semiconductor resistor 2.sub.n and the ground.
Denoted 4 is a zero-cross detection circuit connected to the input terminal 1 which detects when the input signal supplied to the input terminal 1 becomes zero and outputs a timing signal.
Reference numeral 5 represents a control signal input terminal to which a control signal is supplied; and number 6 represents a volume control circuit which issues a switching control signal for controlling the semiconductor switches 3.sub.1, 3.sub.2, . . . , 3.sub.(n+1) of the semiconductor switch circuit 3 according to the timing signal from the zero-cross detection circuit 4 and the control signal from the control signal input terminal 5.
Denoted 7 is a buffer circuit whose input is connected to the second ends of the semiconductor switches 3.sub.1, 3.sub.2, . . . , 3.sub.(n+1) of the semiconductor switch circuit 3. Reference number 8 indicates an output terminal to which the output of the buffer circuit 7 is supplied.
Now, the operation of this circuit will be described in the following.
First, the input signal supplied to the input terminal 1 is divided by the semiconductor voltage dividing circuit 2, from which attenuation signals having different attenuations, obtained from a single input signal, are output to the semiconductor switch circuit 3.
The input signal is also sent to the zero-cross detection circuit 4, which detects when the input signal becomes zero and issues a timing signal.
Based on the timing signal from the zero-cross detection circuit 4 and the control signal supplied to the control signal input terminal 5, the volume control circuit 6 outputs a switching control signal for controlling the semiconductor switches 3.sub.1, 3.sub.2, . . . , 3.sub.(n+1) of the semiconductor switch circuit 3 to produce a desired attenuation signal. Since only one of the semiconductor switches 3.sub.i (where i=1, 2, . . . , (n+1)) that make up the semiconductor switch circuit 3 conducts, the desired attenuation signal is fed to the buffer circuit 7 where it is impedance-converted before being supplied to the output terminal 8.
With the volume control circuit 6 controlling the semiconductor switch circuit 3 according to the timing signal and the control signal, an attenuation signal, which was obtained by attenuating the input signal supplied to the input terminal 1 to a desired signal level, can be produced at the output terminal 8.
The zero-cross detection circuit 4, since it must detect precisely the instant at which the input signal supplied from the input terminal 1 becomes zero, is required to operate at high speeds.
In the conventional volume apparatus, since the voltage dividing circuit and the switch circuit are formed of semiconductors, distortions consisting mainly of second harmonic components are superimposed upon the attenuation signals. Further, the buffer circuit 7 has a high-impedance input and operates at high speeds, so that the attenuation signals are likely to be superimposed with noise which is generated by unwanted external radiation and by the zero-cross detection circuit 4 that produces noise containing high-frequency components.
Next, let us describe distortions superimposed on the attenuation signals.
FIG. 4 schematically shows a part of the semiconductor voltage dividing circuit. In the figure, designated R.sub.1, R.sub.2 are semiconductor resistors, V.sub.1 an absolute voltage applied to the semiconductor resistor R.sub.1, V.sub.2 an absolute voltage applied to the semiconductor resistor R.sub.2, V.sub.BR1 a reverse bias voltage applied to the semiconductor resistor R.sub.1, V.sub.BR2 a reverse bias voltage applied to the semiconductor resistor R.sub.2, V.sub.i an input signal voltage, V.sub.o an output signal voltage, and V.sub.r a reference potential for the input signal voltage V.sub.i and the output signal voltage V.sub.o. The following relationship holds: EQU V.sub.1 =(V.sub.i +V.sub.r), V.sub.2 =(V.sub.o +V.sub.r)
First, the reverse bias voltages V.sub.BR1, B.sub.BR2 of the semiconductor resistors R.sub.1, R.sub.2 are assumed to be averages of the resistors' terminal voltages. Then they are given by ##EQU1##
Next, if we let the resistance value of the semiconductor resistors R.sub.1, R.sub.2 when applied only with the reference voltage be R and the rate of change of the reverse bias for unit voltage increment be K (normally 1&gt;&gt;K), then the reverse bias voltage dependency characteristic of the semiconductor resistor R.sub.1, R.sub.2 can be expressed as EQU R.sub.1, R.sub.2 =(1+K.times.V.sub.BR1, V.sub.BR2).times.R (3)
The resistance value of the semiconductor resistors R.sub.1, R.sub.2 increases monotonously when applied with V.sub.BR1 and V.sub.BR2.
From equation (1) and equation (2), EQU R.sub.1 =[1+K.times.[V.sub.r +(V.sub.i +V.sub.o)/2]].times.R(4) EQU R.sub.2 =[1+K.times.(V.sub.r +V.sub.o /2)].times.R (5)
Since EQU V.sub.o =[R.sub.2 /(R.sub.1 +R.sub.2)].times.V.sub.i ( 6)
substituting equation (4) and equation (5) into equation (6) result in EQU V.sub.o =[(K.times.V.sub.o /2+K.times.V.sub.r +1)/(K.times.V.sub.o +K.times.V.sub.i /2+2K.times.V.sub.r +2)].times.V .sub.i ( 7)
Multiplying the both members with (K.times.V.sub.o +K.times.V.sub.i /2+2K.times.V.sub.r +2) and rewriting the equation gives EQU V.sub.o.sup.2 +2(1/K+V.sub.r).times.V.sub.o =(1/K+V.sub.r).times.V.sub.i( 8)
Here if we assume that (1/K+V.sub.r)=1/C.apprxeq.1/K (.BECAUSE.0&lt;K&lt;&lt;1), the left member of the equation (8) can be rewritten as EQU (V.sub.o +1/C).sup.2 =V.sub.i /C+(1/C).sup.2 ( 9)
Rewriting the equation (9) gives ##EQU2##
Therefore, rewriting the equation (8), we obtain EQU V.sub.o =[(1+C.times.V.sub.i).sup.1/2 -1]/C (11)
Performing the Tailer expansion on (1+C.times.V.sub.i).sup.1/2 and rewriting the equation, we obtain EQU V.sub.o =(V.sub.i -K.times.V.sub.i.sup.2 /2+K.sup.2 .times.V.sub.i.sup.3 /8-. . . )/2 (12)
In the above equation (12), since 0&lt;K&lt;&lt;1, the third term (K.sup.2 .times.V.sub.i.sup.3 /8) and the succeeding terms become so small as to be negligible. Hence, the distortion should only need to consider the second harmonic components.